Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain central topic debate. In this work, we report steep slope switching in MoS$_2$ back-gated by single-layer polycrystalline PbZr$_{0.35}$Ti$_{0.65}$O$_3$. devices exhibit current on/off ratios up to 8$\times$10$^6$ within an ultra-low gate voltage window $V_g$ = $\pm$0.5 V and subthreshold swing (SS) as low 9.7 mV decade$^{-1}$ at room temperature, transcending 60 Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals dominant role metastable polar states domain walls enabling NC mode, which is corroborated relation between SS wall density. Our findings shed light on hysteresis-free mechanism operation, providing simple yet effective material strategy developing low-power 2D nanoelectronics.